Fresh Cloud Silicon
Bring the Cloud Inside
The value of manageable gates

Fresh Cloud Silicon

Fresh Cloud Silicon - a stepwise offering that will serve as a complementary addition
to a service providers purpose-built edge infrastructure -
from a business, techonology, and ecosystem perspective.

Fresh Cloud Silicon is a cloud-native software solution handling compute functionality
with logic gates. It will increase versatility to edge buildouts
to address a variety of application use cases.

Fresh Cloud Silicon is fully compatible with IP portfolios, and suports both standalone
and non-standalone frameworks, which will help service
providers to evolve their edge with future-proof technology
while maximizing the reuse of existing investments.



Our Key Benefits

Add webscale technology
Interwork with high-performing logic gates without impacting your sustainable development stream.

Incresase versatility and flexibility
Capture revenue allowing freely roll out discrete extra capacity services.

Enable inclusive innovation
Embrace logic gate openness that extends to general purpose processing platforms.



Main Architecture Capabilities


  • Microservices

    Logic gates become very dynamic platforms capable of adjusting to customer needs.


  • Built ground up

    The flexibility and pace of innovation from software-driven developments applied to logic gates.


  • Webscale

    Brings the capabilities of large-scale cloud computing companies into enterprise data centers.


  • Containerized

    From an application perspective, it fits seamlessly with CI/CD and DEVOPS.

  • Be Part
    Of The
    Story!

Technology Description

Customizable many-cores that scale and fit with user needs.

Node characteristics

Stack machine with various bit widths.

Configurable ALU, RAM, FPU, timer, I/O.

Extensible hardware instruction set.

Internode communication characteristics

Configurable heterogeneous communication topology.

Direct link, FIFO link, router node and shared memory.

Many core characteristics

Configurable node number and interconnection.

Deterministic clock accurate timing capabilities.

Customizable IP interface with FIFOs and I/O.

Development tools

Easily programmable with a static memory subset of Ruby.

Eclipse IDE multi node debugger plugin.

Testbench interface with other languages.

Multi node tools include ISA simulator, code profiling and wave viewers.

Examples


Synthesis with place and route for Xilinx Ultrascale XCVU440 has proved the scalability.

13 cores

Xilinx Artix-35T FPGA Arty Board
(AES-A7MB-7A35T-G)

2 cores

Lattice iCE40 Ultra Breakout Board
(iCE5LP4K-B-EVN)

112 cores

Xilinx Artix 7 XC7A200T FPGA Board
(ZTEX-USB-FPGA Module 2.16)

9 cores

Altera Cyclone IV OpenRisc Board
(ORDB2A-EP4CE22)

4 cores

Lattice MachXO2 Breakout Board
(LCMXO2-7000HE-B-EVN)

Core capacity being tested

Altera Cyclone V Atlas-SoC
(5CSEMA4U23C6N Terasic P0419 P0286)

Made in Barcelona


Jaume Masip-Torne

Since 1995 working on parallel programming in the research areas of packet switching, optical networking, audio fingerprinting and FPGAs. Likes running on ancient trails through Priorat vineyards.


Ismael Merodio-Codinachs

20 years of VLSI/FPGA and electronic background in telecommunications, broadcast, automotive and medical industrial sectors. Likes to learn the parallelism both in Ruby and HDL (Hardware Description Languages).

Contact Us

email: info@fresh-mc.com